A Robust Multilevel Inverter Topology for Operation under Fault Conditions

Abstract

Multilevel inverters (MLIs) are new demanding topologies that have low total harmonic distortion (THD) and low voltage stress across the switches make them ideal for medium and high-power applications. The authenticity of semiconductor devices is one of the main concerns for these MLIs to operate properly. With an increment in the number of switches in multilevel inverters, the pos-sibility of the fault also arises. Hence, a reliable 5- level inverter topology with fault-tolerant ability has been proposed. The proposed topology can withstand against of Open Circuit (OC) fault caused when any single switch fails. The proposed configuration is fault-tolerant and reliable as compared to the conventional multilevel inverters. Simulation of the proposed topology is done in MATLAB-Simulink and PLECS software packages, and the results obtained for normal (pre-fault), during the fault, and post-fault conditions are discussed. Experimental results also prove the proposed cell topology's robustness and effectiveness in tolerating OC faults across the switches. Furthermore, a thorough comparison is provided to demonstrate the superiority of the proposed topology in comparison to recently published topologies that have fault-tolerant features